1. Field of the Invention
This invention relates to non-volatile memory devices and is more particularly concerned with certain apparatus and methods based on new concepts of memory state demarcation and programming reference signal generation for multi-bit electrically alterable non-volatile memory (EANVM) cells.
2. Related Background Art
In conventional single-bit per cell memory devices, the memory cell assumes one of two information storage states, either an xe2x80x9conxe2x80x9d state or an xe2x80x9coffxe2x80x9d state. This combination of either xe2x80x9conxe2x80x9d or xe2x80x9coffxe2x80x9d defines one bit of information. A memory device using such single-bit cells to store n bits of data (n being an integer greater than 0) thus requires n separate memory cells.
Increasing the number of bits which can be stored in a single-bit per cell memory device involves increasing the number of memory cells on a one-for-one basis with the number of bits of data to be stored. Methods for increasing the number of memory cells in a single memory device have relied upon advanced manufacturing techniques that produce larger chips containing more memory cells or that produce smaller memory cells (e.g., by high resolution lithography) to allow more memory cells to be placed in a given area on a single chip.
An alternative to the single-bit per cell approach involves storing multiple bits of data in a single memory cell. Previous approaches to implementing multiple-bit per cell non-volatile memory devices have typically involved mask-programmable read only memories (ROMs). In one of these approaches, the channel width and/or length of the memory cell is varied such that 2n different conductivity values are obtained which correspond to 2n different states, whereby n bits of data can be stored by a single memory cell. In another approach, the ion implant for the threshold voltage is varied such that the memory cell will have 2n different voltage thresholds (Vt) corresponding to 2n different conductivity levels corresponding to 2n different states, whereby n bits of data can be stored by a single memory cell. Examples of memory devices of these types are described in U.S. Pat. No. 4,192,014 to Craycraft, U.S. Pat. No. 4,586,163 to Koike, U.S. Pat. No. 4,287,570 to Stark, U.S. Pat. No. 4,327,424 to Wu, and U.S. Pat. No. 4,847,808 to Kobatake.
Electrically alterable non-volatile memory (EANVM) devices capable of storing multiple bits of data per cell are also known. In these devices, the multiple memory states of the cell are demarcated by predetermined reference signal levels that define boundaries between adjacent memory states. The memory cell is read out by comparing a signal from the cell with the reference signals to determine the relative levels of the cell signal and the reference signals. The comparison results indicate whether the cell signal level is above or below the respective memory state boundaries, and thus collectively indicate the programmed state of the cell corresponding to the stored data. The comparison results are encoded to reproduce the stored data and complete the cell readout operation. Generally speaking, the number of reference levels required to demarcate n memory states for storing n bits of data is 2nxe2x88x921. The number may be greater if, for example, the uppermost or lowermost memory state is to be bounded on both sides.
Previous approaches to programming multi-bit EANVM cells are based on a repeated cycle of programming and readout of the cell. The cell is programmed incrementally, by the application of programming pulses, and the programmed status of the cell is checked repeatedly during the programming process by reading out the memory state of the cell as described above to verify the attained level of programming. Programming is continued until the target memory state has been reached, as indicated by the readout of the cell.
In order to minimize the possibility of readout errors, the programming level of a multi-bit EANVM cell should be set with a margin relative to the reference signal level or levels that demarcate the target memory state. The programming margin should be sufficient to avoid readout errors that might occur due to variations in operating characteristics of the cell with changing conditions such as temperature, system voltages, or mere passage of time. More particularly, if the cell is programmed too close to a memory state boundary, slight variations in the operating characteristics could shift the cell signal level relative to the state boundary level, resulting in an error upon subsequent readout of the cell.
Program margining is not particularly problematical in single-bit per cell memory devices, since there are only two memory states, and thus no intermediate memory states. Because it is impossible to overshoot the target state by overprogramming the cell, the cell may simply be programmed to set the cell signal level as far as possible from the reference level bounding the two memory states.
By contrast, the presence of one or more intermediate memory states makes program margining a significant concern in the case of multi-bit per cell devices, because an intermediate memory state requires a programming margin that provides adequate separation from two boundary levels-that is, the boundaries of the intermediate memory state with both the state above and the state below. Programming the cell too close to either level can result in a readout error. Also, both overprogramming and under programming must be avoided to prevent overshooting and undershooting the target intermediate state.
Previous program margining techniques include techniques that, for programming purposes, shift the cell signal level or the reference signal levels relative to their values during normal memory readout. The effect in either case is that, for a given programming amount of the cell, the cell will read differently during programming than during a normal readout operation. The difference corresponds to the shift amount of cell signal or the reference signals and provides a programming margin. Examples of these techniques are found in U.S. Pat. No. 5,172,338 to Mehrotra et al. and in Beliker et al., xe2x80x9cA Four-State EEPROM Using Floating-Gate Memory Cells,xe2x80x9d IEEE Journal of Solid State Circuits, Vol. SC-22, No. 3, June 1987, pp. 460-463.
Another margining technique involves the provision of additional reference signals having levels intermediate those of the state-demarcating reference levels. The intermediate reference levels define program margin ranges in conjunction with the state-demarcating levels. After the cell reaches the target memory state, as indicated by comparison with the state-demarcating signals, programming is continued based on further comparison of the cell signal with one or more intermediate reference signals to provide a programming margin. An example of this technique is found in U.S. Pat. No. 4,964,079 to Devin.
In the above-described approaches to programming multi-bit per cell EANVM devices, the programming speed (total time to program a cell to a target state) is substantially limited by the need for repeated readout of the memory cell during the programming process. Also, the aforementioned program margining techniques impose substantial complications on the overall circuit design due to the need to shift the cell signal level or the state-demarcating reference signal levels, or to provide intermediate reference levels for establishing program margin ranges in conjunction with the state-demarcating reference signal levels. Furthermore, these margining techniques do not assure an optimum programming margin throughout variations in operating characteristics of the cell, because they do not precisely track such variations with changing conditions that affect the operating characteristics.
The predecessor applications underlying the present application disclose a completely different approach to multi-bit per cell EANVM programming (the approach is also described in detail herein). According to this approach, the programming control scheme uses a programming reference signal corresponding to the target memory state to program the memory cell, and does not require reading out the memory state of the cell during programming.
The invention claimed in the present application is based on new concepts of memory state demarcation and programming reference signal generation that can be applied with great advantage to the aforementioned approach. According to a first of these concepts, a plurality of programming reference signals (or signals set in substantial correspondence therewith) are used to generate the state demarcating reference signals. This is done in such a manner that each programming reference signal (or correspondingly set signal) has a level unique to its corresponding memory state. As will be more fully appreciated from the detailed description that follows, by generating the state-demarcating reference signals in this manner, it becomes possible to program a multi-bit EANVM cell without reading out the cell""s memory state during the programming operation, while at the same time providing effective program margining without the complexities associated with the previous margining techniques described above.
According to one of its broader aspects, the present invention thus provides an apparatus for demarcating memory states of an EANVM cell having more than two memory states. The apparatus comprises a reference signal generating circuit which generates a plurality of signals corresponding to memory states of the cell, each signal having a level unique to its corresponding memory state and substantially the same as a programming reference level for controlling programming of the cell to the corresponding memory state. The reference signal generating circuit uses the plurality of signals to generate reference signals having levels that constitute boundaries of memory states of the cell.
The invention also provides a programmable multi-level memory apparatus, which comprises an EANVM cell having more than two memory states, a programming circuit for programming the EANVM cell, and a reference signal generating circuit as described above.
According to another of its broader aspects, the present invention provides an apparatus for demarcating memory states of an EANVM cell having more than two memory states, the apparatus comprising a reference signal generating circuit which generates reference signals having levels that constitute boundaries of memory states of the cell. The reference signals are generated dependent upon a plurality of signal levels that are set in substantial correspondence with programming reference levels for controlling programming of the cell, with each programming reference level being unique to a different memory state of the cell.
The invention also provides a programmable multi-level memory apparatus, which comprises an EANVM cell having more than two memory states, a programming circuit for programming the cell, and a reference signal generating circuit as just described.
In a preferred mode of the invention, the plurality of signals used to generate state-bounding the reference signals are themselves generated by reference cells that substantially track changes in operating characteristics of the EANVM cell with changes in conditions that affect the operating characteristics. The reference cells may have substantially the same construction as the EANVM cell, and be manufactured concurrently with the EANVM cell, by the same fabrication process, as elements of the same integrated circuit with the EANVM cell. Thus, the signals that are used to generate the state-bounding reference signals can track changes in the operating characteristics of the EANVM cell with high accuracy. This makes it possible to maintain optimum programming margins throughout variations in operating characteristics of the EANVM cell.
Another new concept of the present invention relates to programming reference signal generation, and in particular the use of reference cells for this purpose. According to this concept, which may (but need not be) applied in conjunction with the first concept discussed above, the programming reference signals are generated by corresponding reference cells which substantially track changes in operating characteristics of the EANVM cell with changes in conditions that affect the characteristics. This assures a stable relationship between the cell signal level and the programming reference signal levels and leads to better programming consistency.
Thus, in accordance with yet another of its broader aspects, the present invention provides a programmable multi-level memory apparatus which comprises an EANVM cell having more than two memory states, a programming reference signal generating circuit, and a programming circuit. The programming reference signal generating circuit includes a plurality of reference cells which substantially track changes in operating characteristics in the EANVM cell with changes in conditions that affect the operating characteristics. The reference cells include a corresponding reference cell for each memory state, with each reference cell being programmed such that the programming reference signal generating circuit generates a programming reference signal having a level unique to the corresponding memory state. The programming circuit selectively programs the EANVM cell in accordance with the level of each programming reference cell.
Still further aspects of the invention relate to the methodology of demarcating memory states of a multi-level EANVM cell based on the principles discussed above.
The principles of the present invention, as well as its various aspects, features, and advantages, will be more fully appreciated from the following detailed description taken in conjunction with the accompanying drawings.